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<div class="title">RTC_TypeDef结构体 参考<div class="ingroups"><a class="el" href="group___c_m_s_i_s.html">CMSIS</a> &raquo; <a class="el" href="group__wb32l003.html">Wb32l003</a> &raquo; <a class="el" href="group___device___peripheral__peripherals.html">Device_Peripheral_peripherals</a></div></div>  </div>
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成员变量</h2></td></tr>
<tr class="memitem:a10e4b0d52a1683e587437b67bdf0efc5"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_t_c___type_def.html#a10e4b0d52a1683e587437b67bdf0efc5">CR</a></td></tr>
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<tr class="memitem:a73d0284f6de3b2e6887a95520777a4a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_t_c___type_def.html#a73d0284f6de3b2e6887a95520777a4a2">TIME</a></td></tr>
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<tr class="memitem:ab05f97ed8a1bf9e25405c114910e84df"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_t_c___type_def.html#ab05f97ed8a1bf9e25405c114910e84df">RCLKTRIM</a></td></tr>
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<h2 class="groupheader">结构体成员变量说明</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ab3619020edfb702a34bd1c69caa9d734">&#9670;&nbsp;</a></span>ALM1DATE</h2>

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<p>RTC date alarm register, Address offset: 0x014 </p>

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<a id="a22ac917fd03f22a54e5afbca28f40316"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a22ac917fd03f22a54e5afbca28f40316">&#9670;&nbsp;</a></span>ALM1TIME</h2>

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<p>RTC Time alarm register, Address offset: 0x010 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2581b40027674d09b5db0dd64f7af282">&#9670;&nbsp;</a></span>ALM2PRD</h2>

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<p>RTC cycle alarm register, Address offset: 0x018 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a113498def9610aa21d4a8400cfef1335">&#9670;&nbsp;</a></span>CLKCR</h2>

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<p>RTC clock control register, Address offset: 0x004 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a10e4b0d52a1683e587437b67bdf0efc5">&#9670;&nbsp;</a></span>CR</h2>

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<p>RTC control register, Address offset: 0x000 </p>

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<p>RTC date register, Address offset: 0x00C </p>

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<a id="a6257a1dba4f7f3f833c7fe9c66a5713f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6257a1dba4f7f3f833c7fe9c66a5713f">&#9670;&nbsp;</a></span>INTCLR</h2>

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          <td class="memname">__IOM uint32_t INTCLR</td>
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<p>RTC status clear register, Address offset: 0x024 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a20253899eaa7c70a011bc5a546983197">&#9670;&nbsp;</a></span>ISR</h2>

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<p>RTC initialization and status register, Address offset: 0x020 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab05f97ed8a1bf9e25405c114910e84df">&#9670;&nbsp;</a></span>RCLKTRIM</h2>

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<p>RTC clock tuning register, Address offset: 0x01C </p>

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<a id="a73d0284f6de3b2e6887a95520777a4a2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a73d0284f6de3b2e6887a95520777a4a2">&#9670;&nbsp;</a></span>TIME</h2>

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<p>RTC time register, Address offset: 0x008 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aeb147441ad599c842acc2f356871d183">&#9670;&nbsp;</a></span>WPR</h2>

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<p>RTC write protect register, Address offset: 0x028 </p>

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